1. Field of the Invention
This invention relates to a semiconductor memory device using transistors as memory cells, and more particularly to a semiconductor memory device employing with memory cells capable of erasing and rewriting data.
2. Description of the Related Art
In some of erasable programmable nonvolatile memory devices such as EPROMs, a basic memory cell is composed of a stacked-gate MOS transistor, where data is written by injection of hot electrons from the drain, while it is erased by applying high voltage to the source to cause tunnel current. Memory cells of this type are usually known as EPROM tunnel oxide memory cells (hereinafter, referred to as ETOX cells), whose cross section is shown in FIG. 1A.
In FIG. 1A, numeral 101 indicates a substrate, 102 a source, 103 a drain, 104 a floating gate, and 105 a control gate.
Data is written into an ETOX cell of such a structure in the same way as an ordinary EPROM cell. Specifically, as shown in FIG. 1B, a low voltage of, for example, 0 V as the source voltage V.sub.S is applied to the source 102; a high voltage as the drain voltage V.sub.D to the drain 103; and a high voltage as the control gate voltage V.sub.CG to the control gate 105. Under these voltage conditions, ON current flows between the source and drain, generating pairs of hot electrons and holes in the vicinity of the drain. The hot electrons are injected into the floating gate 104, which raises the threshold of the transistor, thereby completing the write operation. On the other hand, the holes flow into the substrate 101 as substrate current. The erasing of data is done by applying a high voltage to the source 102 and a low voltage of, for example, 0 V to the control gate 105, which sets the drain 103 to a floating state, as shown in FIG. 1C. The floating gate potential depends on the source voltage and the capacitance ratio of the capacitance between the control gate 105 and floating gate 104 and the capacitance between the floating gate 104 and source 102. With this floating gate potential, Fowler-Nordheim tunnel current flows between the floating gate 104 and source 102, which extracts electrons from the floating gate 104, thereby completing the erase operation.
In conventional EEPROMs Electrically Erasable Programmable ROMs) using the ETOXs, data is written on a bit basis, while it is erased on an all-bit basis (flush erasure). This is because in constructing a memory cell array through a conventional single-layer metal process, a significantly large size chip is required to erase data in small blocks, leading to unreasonably high cost.
FIG. 2 is a circuit diagram of a memory cell array section in a conventional EEPROM employing the FIG. 1A memory cell. In the figure, numeral 11, . . . , 11 indicate ETOX cells arranged in matrix, 12, . . . , 12 word lines connected to the gates of ETOX cells 11 on a row basis, 13, . . . , 13 common source diffused interconnections composed of diffused regions and connected to the sources of the ETOX cells 11 on a two adjacent row basis, 14, . . . , 14 source interconnections made of a metal such as aluminum electrically connecting the individual common source diffused interconnections 13 to one another, and 15, . . . , 15 bit lines made of a metal such as aluminum connected to the drains of the ETOX cells 11 on a column basis. The EEPROM is assumed to allow a plurality of bits to be read from or written into in parallel simultaneously. Therefore, the ETOX cells 11 are divided into groups of a specified number of parallel bits on a bit line basis, and the bit lines 15 are each connected to sense amplifiers via column select transistors 16.
FIG. 3 is a pattern layout for a integrated circuit of the memory cell array of FIG. 2. FIG. 4 is a sectional view through line A--A.sub.a of FIG. 3. In this example, a p-type silicon substrate 21 is used as semiconductor substrate, and the ETOX cells are of the n-channel type. In FIG. 4, numeral 22 indicates a first gate insulating film of an ETOX cell; 23 a floating gate; 24 a second gate insulating film; 25 a control gate composed of, for example, a layer of polysilicon, and constituting the word line 12; 26 an n.sup.+ -type diffused region constituting the common source and the common source diffused interconnection 13; 27 an n.sup.+ -type diffused region serving as the common drain of two adjacent ETOXs in the column direction; 28 a metal interconnection serving as the source interconnection 14 made of, for example, aluminum, and connected to the n.sup.+ -type diffused region 26; 29 a contact hole connecting the metal interconnection 28 to the n.sup.+ -type diffused region 26; 30 an interlayer insulating film covering the control gate; 31 a metal inter connection made of, for example, aluminum, serving as the bit line 15, and connected to the n.sup.+ -type diffused region 27 serving as the common drain; and 32 a contact hole connecting the metal interconnection 31 to the n.sup.+ -type diffused region 27.
With this arrangement, the drain potential of each ETO cell is normally applied via the aluminum bit line 15; the gate potential (control gate potential) is applied via the word line 12 extending in the direction crossing the bit line 15; and the source potential is applied via the common source diffused line 13 extending in the direction parallel with the word line 12. The resistance of the common source diffused interconnection 13 is higher than that of a metal interconnection such as aluminum, which has the same effect of inserting resistance R in the common source interconnection 13 as shown in FIG. 2. For this reason, source interconnections 14 of low-resistance aluminum are connected to the source diffused interconnection 13 at a suitable number of places in order to apply the source potential to the common source diffused interconnection 13 in a distributed manner.
With this EEPROM, write operation is based on the same principle as that explained in FIG. 1B with a high voltage selectively applied to one bit line 15 and one word line 12, and the ground potential to the common source diffused interconnection 13. Erase operation is based on the same principle as that explained in FIG. 1C by grounding all the word lines 12 and putting the column select transistor 16 in the off state to put all the bit lines 15 in a floating state while applying a high voltage to the common source diffused interconnection. That is, because of memory layout restrictions, all bits are erased simultaneously (flush erasure).
As noted above, with conventional EEPROMs using ETOX cells, layout restrictions merely permits all bits or a block of many bits to be erased at a time. To erase data in much smaller memory blocks, it is necessary to significantly increase the chip size. The reason for this will be explained below.
For example, in a flush-erase-type EEPROM of one megabits, the minimum unit will be considered for a case where the memory cells are divided into blocks, in which blocks data is erased. Ordinary 1-megabit memory arrays have a rectangular matrix of 1 kilo rows.times.1 kilo columns. A bit string to be written or read has a length of 8 bits or 16 bits like ordinary EPROMs. Since the sense amplifiers for data read are located on the column side, the memory cell array has a structure of 1 kilo rows.times.128 columns.times.8 bits or 1 kilo rows.times.64 columns.times.16 bits.
Now, consideration will be given to a case where the source potential previously applied to the common source diffused interconnection 13 shared by all bits is applied to the individual aluminum source interconnections 14 independently. Specifically, in FIG. 2, the common source diffused line 13 shared by the sources in the column direction is divided into blocks at intervals of, for example, eight bit lines, and each block is independently applied with the source potential. In this case, source interconnections 14 are provided at a rate of eight bit lines per source interconnection. If eight-bit strings are used, the minimum block unit will be as large as 1 kilo/1 column.times.8 column .times.8 bits=64 kilobits. An attempt to divide memory cells into still smaller blocks requires more source interconnections 14, resulting in a larger chip size.
Users want data erasure in much smaller blocks. For example, in the field of magnetic disk memory devices, a single track is divided into 512-byte units and all operating systems (OS) are also based on 512-byte units. To apply flush-erase-type EEPROMs to this field, it is necessary to change such OS, which is technically difficult. Another problem with flush-erase-type EEPROMs is the time required to rewrite data. The time required to write one megabits of data is generally approximately 15 seconds, provided that the write time per bit is 100 .mu.s. Thus, to rewrite only a small amount of data involves first erasing all bits and then writing the data spending 15 seconds, which would have an adverse effect on applications.
There is still another problem with EEPROMs: repetition of erase/write (E/W) cycles is limited. This is because repetition of erase/write operations permits charges to be trapped in the gate insulating film, aggravating the characteristics gradually. The characteristics of memory cells is normally guaranteed for as many as 10 4 times of E/W cycles. Therefore, it is desirable to erase data in smaller blocks. Erasure in smaller blocks prevents extra electrical stress from being applied to the memory cells not to be rewritten, which helps improve the overall reliability of the device.